Non-volatile memory having individually optimized silicide contacts and process therefor

ABSTRACT

In an integrated-circuit memory, performance is increased by reducing an electrical contact resistance between a metal layer and an upper poly layer (a control gate poly). The electrical contact resistance is reduced by increasing the thickness of a silicide layer between the metal layer and the upper poly layer. The memory has a memory cell region and a non-memory cell region. The thickness of the silicide layer is typically restricted by consideration of integrated-circuit fabrication geometry for each memory cell not to exceed a predetermined aspect ratio. The present implementation allows independent optimization of the thickness of silicide layer in the memory cells region and the non-memory cell region. In particular, in the non-memory cell region, a thicker silicide layer significantly improves the contact resistance of a slit contact for components having the upper poly layer in contact with a lower poly layer (a floating gate poly).

BACKGROUND

This application relates generally to two- or three-dimensionalnonvolatile memory integrated circuits such as semiconductor flashmemory and its fabrication, and more specifically, to ones havingdifferent low resistance metal silicide contacts optimized for differentportions of the integrated circuits.

Solid-state memory capable of nonvolatile storage of charge,particularly in the form of EEPROM and flash EEPROM packaged as a smallform factor card, has become the storage of choice in a variety ofmobile and handheld devices, notably information appliances and consumerelectronics products. Unlike RAM (random access memory) that is alsosolid-state memory, flash memory is non-volatile, and retains its storeddata even after power is turned off. Also, unlike ROM (read onlymemory), flash memory is rewritable similar to a disk storage device. Inspite of the higher cost, flash memory is increasingly being used inmass storage applications.

Flash EEPROM is similar to EEPROM (electrically erasable andprogrammable read-only memory) in that it is a non-volatile memory thatcan be erased and have new data written or “programmed” into theirmemory cells. Both utilize a floating (unconnected) conductive gate, ina field effect transistor structure, positioned over a channel region ina semiconductor substrate, between source and drain regions. A controlgate is then provided over the floating gate. The threshold voltagecharacteristic of the transistor is controlled by the amount of chargethat is retained on the floating gate. That is, for a given level ofcharge on the floating gate, there is a corresponding voltage(threshold) that must be applied to the control gate before thetransistor is turned “on” to permit conduction between its source anddrain regions. Flash memory such as Flash EEPROM allows entire blocks ofmemory cells to be erased at the same time.

The floating gate can hold a range of charges and therefore can beprogrammed to any threshold voltage level within a threshold voltagewindow. The size of the threshold voltage window is delimited by theminimum and maximum threshold levels of the device, which in turncorrespond to the range of the charges that can be programmed onto thefloating gate. The threshold window generally depends on the memorydevice's characteristics, operating conditions and history. Eachdistinct, resolvable threshold voltage level range within the windowmay, in principle, be used to designate a definite memory state of thecell.

Nonvolatile memory devices are also manufactured from memory cells witha dielectric layer for storing charge. Instead of the conductivefloating gate elements described earlier, a dielectric layer is used.Such memory devices utilizing dielectric storage element have beendescribed by Eitan et al., “NROM: A Novel Localized Trapping, 2-BitNonvolatile Memory Cell,” IEEE Electron Device Letters, vol. 21, no. 11,November 2000, pp. 543-545. An ONO dielectric layer extends across thechannel between source and drain diffusions. The charge for one data bitis localized in the dielectric layer adjacent to the drain, and thecharge for the other data bit is localized in the dielectric layeradjacent to the source. For example, U.S. Pat. Nos. 5,768,192 and6,011,725 disclose a nonvolatile memory cell having a trappingdielectric sandwiched between two silicon dioxide layers. Multi-statedata storage is implemented by separately reading the binary states ofthe spatially separated charge storage regions within the dielectric.

There are many commercially successful semiconductor memory devicesbeing used today. These semiconductor memory devices include volatilememory devices, such as dynamic random access memory (“DRAM”) or staticrandom access memory (“SRAM”) devices, non-volatile memory devices, suchas resistive random access memory (“ReRAM”), electrically erasableprogrammable read only memory (“EEPROM”), flash memory (which can alsobe considered a subset of EEPROM), ferroelectric random access memory(“FRAM”), and magneto-resistive random access memory (“MRAM”), and othersemiconductor elements capable of storing information. Furthermore, eachtype of memory device may have different configurations. For example,flash memory devices may be configured in a NAND or a NOR configuration.

The memory devices can be formed from passive and/or active elements, inany combinations. By way of non-limiting example, passive semiconductormemory elements include ReRAM device elements, which in some embodimentsinclude a resistivity switching storage element, such as an anti-fuse,phase change material, etc., and optionally a steering element, such asa diode, etc. Further by way of non-limiting example, activesemiconductor memory elements include EEPROM and flash memory deviceelements, which in some embodiments include elements containing a chargestorage region, such as a floating gate, conductive nanoparticles or acharge storage dielectric material.

Multiple memory elements may be configured so that they are connected inseries or such that each element is individually accessible. By way ofnon-limiting example, NAND devices contain memory elements (e.g.,devices containing a charge storage region) connected in series. Forexample, a NAND memory array may be configured so that the array iscomposed of multiple strings of memory in which each string is composedof multiple memory elements sharing a single bit line and accessed as agroup. In contrast, memory elements may be configured so that eachelement is individually accessible, e.g., a NOR memory array. One ofskill in the art will recognize that the NAND and NOR memoryconfigurations are exemplary, and memory elements may be otherwiseconfigured.

The semiconductor memory elements of a single device, such as elementslocated within and/or over the same substrate or in a single die, may bedistributed in two or three dimensions, such as a two dimensional arraystructure or a three dimensional array structure.

In a two dimensional memory structure, the semiconductor memory elementsare arranged in a single plane or single memory device level. Typically,in a two dimensional memory structure, memory elements are located in aplane (e.g., in an x-z direction plane) which extends substantiallyparallel to a major surface of a substrate that supports the memoryelements. The substrate may be a wafer over which the layers of thememory elements are deposited and/or in which memory elements are formedor it may be a carrier substrate which is attached to the memoryelements after they are formed.

The memory elements may be arranged in the single memory device level inan ordered array, such as in a plurality of rows and/or columns.However, the memory elements may be arranged in non-regular ornon-orthogonal configurations as understood by one of skill in the art.The memory elements may each have two or more electrodes or contactlines, such as bit lines and word lines.

A three dimensional memory array is organized so that memory elementsoccupy multiple planes or multiple device levels, forming a structure inthree dimensions (i.e., in the x, y and z directions, where the ydirection is substantially perpendicular and the x and z directions aresubstantially parallel to the major surface of the substrate).

As a non-limiting example, each plane in a three dimensional memoryarray structure may be physically located in two dimensions (one memorylevel) with multiple two dimensional memory levels to form a threedimensional memory array structure. As another non-limiting example, athree dimensional memory array may be physically structured as multiplevertical columns (e.g., columns extending substantially perpendicular tothe major surface of the substrate in the y direction) having multipleelements in each column and therefore having elements spanning severalvertically stacked memory planes. The columns may be arranged in a twodimensional configuration, e.g., in an x-z plane, thereby resulting in athree dimensional arrangement of memory elements. One of skill in theart will understand that other configurations of memory elements inthree dimensions will also constitute a three dimensional memory array.

By way of non-limiting example, in a three dimensional NAND memoryarray, the memory elements may be connected together to form a NANDstring within a single horizontal (e.g., x-z) plane. Alternatively, thememory elements may be connected together to extend through multiplehorizontal planes. Other three dimensional configurations can beenvisioned wherein some NAND strings contain memory elements in a singlememory level while other strings contain memory elements which extendthrough multiple memory levels. Three dimensional memory arrays may alsobe designed in a NOR configuration and in a ReRAM configuration.

A monolithic three dimensional memory array is one in which multiplememory levels are formed above and/or within a single substrate, such asa semiconductor wafer. In a monolithic three-dimensional array thelayers of each level of the array are formed on the layers of eachunderlying level of the array. One of skill in the art will understandthat layers of adjacent levels of a monolithic three dimensional memoryarray may be shared or have intervening layers between memory levels. Incontrast, two dimensional arrays may be formed separately and thenpackaged together to form a non-monolithic memory device. For example,non-monolithic stacked memories have been constructed by forming memorylevels on separate substrates and adhering the memory levels atop eachother. The substrates may be thinned or removed from the memory levelsbefore bonding, but as the memory levels are initially formed overseparate substrates, such memories are not monolithic three dimensionalmemory arrays. Further, multiple two dimensional memory arrays or threedimensional memory arrays (monolithic or non-monolithic) may be formedseparately and then packaged together to form a stacked-chip memorydevice.

Semiconductor devices typically have one or more polysilicon layer asgate electrode material for devices. A polysilicon gate's electricalconductivity may be increased by depositing a metal (such as tungsten)or a metal silicide (such as tungsten silicide) over the gate.Polysilicon may also be employed as a conductor or as an ohmic contactfor shallow junctions, with the desired electrical conductivity attainedby doping the polysilicon material.

For example, in a NAND memory device, memory cells and other circuitelements are formed on the same wafer. Typically, depositions ofpolysilicon/metal silicide/metal contact are performed across the wafer.A configuration of polysilicon/metal silicide/metal contact may beoptimized for the memory cells but not for the other circuit elements.This may result in higher than optimal resistances in the metal contactsof the other circuit elements.

Thus, there is a need to provide a memory device and processing methodwhere the configuration of silicide is independently optimized for thememory cells and for the other circuit elements to provide lower contactresistance for the other circuit elements.

SUMMARY

In an integrated-circuit memory, performance is increased by reducing anelectrical contact resistance between a metal layer and an upper orfirst poly layer (a control gate poly). The electrical contactresistance is reduced by increasing the thickness of a silicide layerbetween the metal layer and the upper poly layer. The memory has amemory cell region and a non-memory cell region. The thickness of thesilicide layer is typically restricted by consideration ofintegrated-circuit fabrication geometry for each memory cell not toexceed a predetermined aspect ratio. The present implementation allowsindependent optimization of the thickness of silicide layer in thememory cells region and the non-memory cell region. In particular, inthe non-memory cell region, a thicker silicide layer significantlyimproves the contact resistance of a slit contact for components havingthe upper poly layer in contact with a lower poly layer (a floating gatepoly).

The thicker silicide layer in the non-memory cell region is accomplishedby a self-aligned silicide process. The process includes using a masklayer to open a trench in the non-memory cell region that extends fromthe upper first poly layer to the lower poly layer, depositing a secondpoly layer, etching back the second poly layer to the mask layer,depositing a first metal layer and annealing to form a first silicidelayer between the first metal layer and the second poly layer, removingthe first metal layer and the mask layer to expose the first poly layer,and depositing a second metal layer and annealing to form a secondsilicide layer between the second metal layer and the first poly layer.In this way, regions masked by the mask layer have the second silicidelayer and regions unmasked by the mask layer has a combined first andsecond silicide layer.

The non-memory cell region includes a component with a slit contact. Thestep of etching back the second poly layer to the mask layer to exposethe first poly layer also expose a portion the lower poly layer. Thestep of depositing a second metal layer and annealing to form a secondsilicide layer between the second metal layer and the first poly layerand also between the second metal layer and the lower poly layer.

Various aspects, advantages, features and embodiments are included inthe following description of exemplary examples thereof, whichdescription should be taken in conjunction with the accompanyingdrawings. All patents, patent applications, articles, otherpublications, documents and things referenced herein are herebyincorporated herein by this reference in their entirety for allpurposes. To the extent of any inconsistency or conflict in thedefinition or use of terms between any of the incorporated publications,documents or things and the present application, those of the presentapplication shall prevail.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a host in communication with a memory device in whichthe features of the present invention are embodied.

FIG. 2 illustrates an example memory organization in the NANDconfiguration in which a page of memory cells is sensed or programmed inparallel.

FIG. 3 illustrates schematically a conventional semiconductor structurefor realizing the example NAND memory of FIG. 2.

FIG. 4 illustrates schematically an example of a conventional slitcontact for the peripheral circuits.

FIG. 5 illustrates schematically a further modification to the slitcontact shown in FIG. 4.

FIG. 6 illustrates a memory device with the metal silicide layer beingof different thickness for the different types of device element.

FIG. 7 is a cross-sectional view of a slab, which constitutes the grossstructure after the first part of the fabrication.

FIG. 8 is a cross-sectional view of the slab, illustrating the processof cutting trenches in the slab for poly plugs formation later.

FIG. 9 is a cross-sectional view of the slab, illustrating the processof depositing a layer of CG 2 poly 410.

FIG. 10 is a cross-sectional view of the slab, illustrating the processof forming the poly plug in the select transistor region.

FIG. 11 is a cross-sectional view of the slab, illustrating the processof depositing a layer of metal 360 on top of the poly plug and the slit.

FIG. 12 is a cross-sectional view of the slab, illustrating the processof forming a first silicide layer 350 and followed by removing the metallayer 360.

FIG. 13 is a cross-sectional view of the slab, illustrating the processof removing the mask 400.

FIG. 14 is a cross-sectional view of the slab, illustrating the processof depositing a layer of metal by sputtering.

FIG. 15 is a cross-sectional view of the slab after, illustrating theprocess of segmenting the slab along the x-direction to provideisolation between memory cells and devices.

DETAILED DESCRIPTION Memory System

FIG. 1 illustrates a host in communication with a memory device in whichthe features of the present invention are embodied. The host 10typically sends data to be stored at the memory device 20 or retrievesdata by reading the memory device 20. The memory device 20 includes oneor more memory chip 30 managed by a memory controller 40. The memorychip 30 includes a memory array 100 of memory cells with each cellcapable of being configured as a multi-level cell (“MLC”) for storingmultiple bits of data, as well as capable of being configured as asingle-level cell (“SLC”) for storing 1 bit of data. The memory chipalso includes peripheral circuits 50 such as row and column decoders,sense modules, data latches and I/O circuits. An on-chip controlcircuitry 60 controls low-level memory operations of each chip. Thecontrol circuitry 60 is an on-chip controller that cooperates with theperipheral circuits 50 to perform memory operations on the memory array100. The control circuitry 60 typically includes a state machine 62 toprovide chip level control of memory operations via data, control andaddress buses 61.

In many implementations, the host 10 communicates and interacts with thememory chip 30 via the memory controller 40. The controller 40co-operates with the memory chip and controls and manages higher levelmemory operations. A firmware 42 provides codes to implement thefunctions of the controller 40. An error correction code (“ECC”)processor (not shown) in the controller processes ECC during operationsof the memory device 20.

For example, in a host write, the host 10 sends data to be written tothe memory array 100 in logical sectors allocated from a file system ofthe host's operating system. A memory block management systemimplemented in the controller stages the sectors and maps and storesthem to the physical structure of the memory array. A preferred blockmanagement system is disclosed in United States Patent ApplicationPublication Number: US-2010-0172180-A1, the entire disclosure of whichis incorporated herein by reference.

Physical Memory Architecture

In order to improve read and program performance, multiple memory cellsor memory transistors in the memory array are read or programmed inparallel. Thus, a “page” of memory cells are read or programmedtogether. In existing memory architectures, a row typically containsseveral interleaved pages or it may constitute one page. All memorycells of a page will be read or programmed together.

Similar, to improve erase performance, a block of memory cells organizedin pages is erased as a unit. The block is sometimes referred to as a“flash” block and a memory with block erase structure is referred to asa “flash” memory.

FIG. 2 illustrates an example memory organization in the NANDconfiguration in which a page of memory cells is sensed or programmed inparallel. FIG. 2 essentially shows a row of NAND strings 110 in thememory array 100 of FIG. 1.

Each NAND string 110 is a series of memory transistors 120 daisy-chainedby their sources and drains to form a source terminal and a drainterminal respective at its two ends. A pair of select transistors 130,140 controls the memory transistors chain's connection to the externalvia the NAND string's source terminal and drain terminal respectively.In the memory array, when the source select transistor 130 is turned onvia a source select line SGS 132, the source terminal is coupled to asource line 150. Similarly, when the drain select transistor 140 isturned on via the drain select line SGD 142, the drain terminal of theNAND string 110 is coupled to a bit line 160 of the memory array. Eachmemory transistor 120 in the NAND string 110 acts as a memory cell 120.The memory cell 120 has a charge storage element 122, such as a floatinggate, to store a given amount of charge so as to represent an intendedmemory state. A control gate 124 of each memory transistor allowscontrol over read and write operations. The control gates 124 ofcorresponding memory transistors 120 among the row of NAND strings areall connected to the same word line 170 (such as one of WL0, WL1, . . .). Similarly, control gates 134, 144 corresponding to the selecttransistors 130, 140 (accessed via select lines SGS 132 and SGD 142respectively) provide control access to the NAND string 110 via itssource terminal and drain terminal respectively.

A “page” such as the page 180, is a group of memory cells 120 enabled tobe sensed or programmed in parallel via a row of bit lines 160. This isaccomplished in the peripheral circuits 50 by a corresponding page ofsense amplifiers 52. The sensed results are latches in a correspondingset of data latches 54. Each sense amplifier can be coupled to a NANDstring, such as NAND string 110 via a bit line, such as bit line 160.For example, the page 180 is along a row and is sensed by a sensingvoltage applied to the control gates 124 of the memory cells 120 of thepage connected in common to the word line WL3. Along each column, eachmemory cell such as memory cell 120 is accessible by a sense amplifiervia a bit line. Data in the data latches 54 are toggled in from or outto the memory controller 40 via the buses 61. The page 180 referred toabove is a physical page memory cells or sense amplifiers. Depending oncontext, in the case where each cell is storing multi-bit data, eachphysical page has multiple data pages.

FIG. 3 illustrates schematically a conventional semiconductor structurefor realizing the example NAND memory of FIG. 2. Semiconducting devicescomprising different types of components are typically formed on asilicon substrate 300. In this case, there are memory cell componentssuch as memory cells 120 and other type of non-memory cell components,such as select transistors 130, 140 and a device element 56 inperipheral circuits 50.

FIG. 3 illustrates a NAND string with four memory cells 120. Theindividual memory cells 120 of the NAND are isolated with oxide inbetween (not shown). Referring also to FIG. 2, for the memory cell 120,essentially the FG poly layer 330 forms the floating gate 122. The CG 1poly layer 340, the silicide layer 350 and the metal layer 360 form thecontrol gate 124.

For the memory cell components, each memory cell 120 is basically afield-effect transistor whose field is further modified by chargesprogrammed into the floating gate 122. Channel regions are formed in thesubstrate 300 by doping source and drain regions 310. A layer of oxide320 provides insulation from the channel region. This is followed by alayer of FG poly 330 to implement a floating gate 122. A gate oxidelayer 322 insulates the floating gate 330 from above. Then a layer of CG1 poly 340 acting as a control gate electrode is placed on top of thegate oxide 322. A composite control gate 124 with improved conductivityis achieved by a layer of metal 360, such as tungsten on top of the CG 1poly 340. Furthermore, the resistance of the metal contact 360 to thecontrol gate electrode 340 is significantly reduced with an interfacingmetal silicide layer 350.

For the non-memory cell components, such as the select transistors 134and 144, they are basically field-effect transistors. They respectivelycontrol the connection of the source and drain terminals of the NANDstring to the external. As they are not memory cells, there is no needfor the FG poly layer 330 that forms the floating gate 122. Thus, forthe non-memory cell components, the existing FG poly layer 330 iselectrically incorporated into the select gate, such as select gate 134,144 or 56. This is accomplished by connecting the composite control gate124 directly to the FG poly layer 330 by a conductive poly plug 372. Thepoly plug is effected by a CG 2 poly 410 filling that effectivelyincorporates the FG poly layer 330 (i.e., the floating gate poly) aspart of a device control gate or select gate 144 or 56.

Similarly for other non-memory cell components, such the peripheralcircuits 50, they include field-effect transistors. Thus, a poly plug374 constituting from the CG 2 poly 410 filling is employed to form anelectrical connection between the existing FG poly layer 330 330 (i.e.,the floating gate poly) and the control gate to form a gross control orselect gate 56.

Generally, the lower the metal contact resistance to the control gateelectrode, the better is the speed performance of the memory device.Earlier, it has been described that an interfacing metal silicide layer350 between the metal layer 360 and the CG 1 poly 340 significantlyreduces the contact resistance. Typically, the thicker the metalsilicide layer 350, the lower is the contact resistance. The metalsilicide layer 350 is formed after deposition of the CG 1 poly layer 340and the metal layer 360 by annealing under elevated temperature to formthe silicide layer 350 at their common interface.

While it is desirable to have a thicker silicide layer 350, however, thememory cell geometry places a limitation on the thickness. As can beseen from FIG. 3, each layer constituting a memory cell 120 requires acertain thickness for optimum functioning and performance. For example,the metal layer 360 needs to be of sufficient thickness to be robust andof low resistance. When all the layers are tallied, the memory cellalready has a column structure with an aspect ratio beyond which “wordline collapse” is liable to occur. Thus, the thickness 352 of the metalsilicide layer 350 as well as that of the metal layer 360 each has anupper limit predetermined by consideration of the geometry of the memorycell (memory cell components) during fabrication, which by extensionalso imposes the same limit on the non-memory cell components as thedeposition of each of the CG 1 poly layer 340 and the metal layer 360 isperformed across the substrate at the same time.

For the peripheral circuits among the non-memory cell components,without the option of further increasing the thickness of the metalsilicide layer 350, one way of reducing the resistance of the metalcontact resistance to the control gate electrode is to form a “slitcontact”. U.S. Pat. No. 8,338,365 B2 discloses a similar slit contact inwhich the metal layer 360 and the silicide layer 350 drop into a trenchor “slit” to make contact with structures closer to or underneath thesubstrate.

FIG. 4 illustrates schematically an example of a conventional slitcontact for the peripheral circuits. A trench or slit is open to accessthe FG Poly layer 330. The metal layer 360 and the silicide layer 350are dropped into and around the trench to form a slit contact 58. Inthis way, contact resistance is reduced owing to the increased contactarea. The slit contact 58 improves over the poly plug 374 shown in FIG.3.

FIG. 5 illustrates schematically a further modification to the slitcontact shown in FIG. 4. As described with regard to FIG. 4, the slitcontact 58 improves over the poly plug 374. Still, the contactresistance could be further improved if the silicide layer 350 has athickness 356 that is greater than the previous thickness 352 shown inFIG. 3 and FIG. 4. However, as explained earlier, this is infeasiblebecause the previous thickness 352 is already optimized and limited byconsiderations in fabricating the memory cells portion of the chip. Theselect transistors are dependent on low contact resistance to switch anentire NAND string. Similar, the performance of the peripheral circuitscould improve with lower contact resistance. A lower resistance in thecircuits generally improves on the operating speed of the memory.

According, it is desirable to have a memory device with a semiconductorstructure in which the different types of device element areindependently optimized.

Silicide in the Memory Cells not Impacted by Thicker Silicide in OtherDevices on the Same Chip

A memory device has a semiconductor structure comprising multiple layerson a substrate. The multiple layers including a floating gate layer, acontrol gate layer, a metal silicide layer and a metal layer. Thesemiconductor structure comprises memory cell components and non-memorycell components.

The memory cell components include non-volatile memory cells. Eachmemory cell has a floating gate layer, a control gate layer, a metallayer and a metal silicide layer interfacing between the control gatelayer and the metal layer.

The non-memory cell components include select transistors withindividual ones sharing similar layer structure as the first type ofdevice element but also with its floating gate electrically connected toits control gate by a connecting plug.

The non-memory cell components also include peripheral circuits, withindividual ones sharing similar layer structure as the first type ofdevice element but also with a slit contact that has the metal layerdips into the floating gate layer. The non-memory cell components arecharacterized by a metal silicide layer having additional thicknesscompared to that of the memory cell components. In this way, the metalsilicide layers for the two types of components are independentlyoptimized. In the case of the select transistors, the additionalthickness in metal silicide layer improves the conductance between themetal layer and the control gate and connected floating gate layers. Inthe case of the peripheral devices, the conductance between the metallayer and the floating gate layer is improved.

FIG. 6 illustrates a memory device with the metal silicide layer beingof different thickness for the different types of device element. Thememory device 30 has a semiconductor structure comprising multiplelayers on a substrate 300. The multiple layers including a floating gatelayer, such as a doped polysilicon layer, FG Poly 330, a control gatelayer, such as a doped polysilicon layer, CG1 Poly 340, a metal silicidelayer 350 and a metal layer 360, such as titanium.

The semiconductor structure comprises memory cell components andnon-memory cell components.

The memory cell components include a non-volatile memory cell 120,having the floating gate layer FG Poly 330, the control gate layer CG1Poly 340, the metal layer 360 and the metal silicide layer 350interfacing between the control gate layer 340 and the metal layer 360.

The non-memory cell components include a select transistor 140, sharingsimilar layer structure as the memory cell components but with itsfloating gate 330 electrically connected to its control gate 340 by aconnector plug 372.

The non-memory cell components also include the peripheral circuits 50.The device element of the peripheral circuits shares similar layerstructure as the memory cell components but with a slit contact 58 thathas the metal layer 360 dips into the floating gate layer 330.

The non-memory cell components are characterized by having a metalsilicide layer 350 of additional thickness compared to that of thememory cell components. In the case of the select transistors, the metalsilicide layer 350′ has a thickness 352′, which is thicker than that ofthe metal silicide layer 350 for the first type of device. In the caseof the device element of the peripheral devices, the metal silicidelayer 350′ has a thickness 352′, which is thicker than that of the metalsilicide layer 350 for the memory cell components. The additionalthickness in metal silicide layer 350′ of the non-memory cell componentsimprove the conductance between the metal layer to the connector plug372 for the select transistor 140 or to the floating gate for the deviceelement of the peripheral circuits 50. As can be seen from FIG. 6, themetal silicide layers 350 and 350′ for the two types of componentscoexisting on the same substrate 300 are independently optimized.

Process

FIG. 7 to FIG. 15 illustrate a self-aligned silicide process of formingindependently optimized metal silicide layer in the structureillustrated in FIG. 6.

For example, a NAND memory device is fabricated on top of asemiconductor substrate to form a memory device chip. The fabricationcomprises of two parts. In the first part is the formation of a grossstructure of the memory device, which includes the memory cellcomponents (e.g., NAND memory cells), and the non-memory cellcomponents. The gross structure and therefore the silicide thickness areprimarily dictated by the requirements of forming the memory cellcomponents (e.g., NAND memory cells). In the second part, additionalprocess steps allow thicker silicide layers to be formed in thenon-memory cell components compared to that in the first-type devices.

FIG. 7 is a cross-sectional view of a slab, which constitutes the grossstructure after the first part of the fabrication. Essentially, a slabhas been formed comprising of multiple layers that correspond to thegross structure of the NAND memory. First, diffusion regions 310 areformed in the substrate 300 for the sources and drains of the memorycells. Then the following layers are deposited in turn on top of eachother. A first layer of insulating oxide 320 is formed on top of thesubstrate 300. A layer of FG (floating gate) poly 330 is formed on topof the oxide 320. A second layer of oxide 322 is formed on top of the FGpoly 330. A layer of CG 1 Poly 340 is formed on top of the second layerof oxide 322. A layer of oxide mask 400 is formed on top of the layer ofCG 1 Poly.

FIG. 8 is a cross-sectional view of the slab, illustrating the processof cutting trenches in the slab for poly plugs formation later. This isaccomplished by unmasking the oxide mask 400 where these poly plugs areto be formed, the sites of select transistor and slit contacts of theperipheral circuits. The trenches runs along the x-direction (not shownexplicitly) and are spaced apart in the y-direction. Anisotropic etchingcut the trenches to a depth reaching the FG poly 330.

FIG. 9 is a cross-sectional view of the slab, illustrating the processof depositing a layer of CG 2 poly 410.

FIG. 10 is a cross-sectional view of the slab, illustrating the processof forming the poly plug in the select transistor region. This isaccomplished by etching back the CG 2 poly 410 to the metal layer 360.This basically leaves a poly plug in the select transistor region and aslit in the slit contact region of the peripheral circuits.

FIG. 11 is a cross-sectional view of the slab, illustrating the processof depositing a first layer of metal 360′ on top of the poly plug andthe slit.

FIG. 12 is a cross-sectional view of the slab, illustrating the processof forming a first silicide layer 350 and followed by removing the firstmetal layer 360′. In the select transistor region, the silicide layer350 is formed at the interface between the first metal layer 360′ andthe poly plug filled with CG 2 Poly 410. In the peripheral circuitsregion, the silicide layer 350 is formed at the interface between thefirst metal layer 360′ and the CG 2 Poly 410 and FG Poly 330. Thesilicide layer 350 is formed by annealing at elevated temperature sothat the poly reacts with the metal to form the silicide. The silicidelayer 350 has a thickness commensurate with the oxide mask 400.

FIG. 13 is a cross-sectional view of the slab, illustrating the processof removing the mask 400. This will expose the CG 1 poly layer 340.

FIG. 14 is a cross-sectional view of the slab, illustrating the processof depositing a second metal layer by sputtering. This is followed by aprocess of forming a silicide layer between the second metal layer 360and the CG 1 poly layer 340 by annealing.

FIG. 15 is a cross-sectional view of the slab after, illustrating theprocess of segmenting the slab along the x-direction to provideisolation between memory cells and devices. Isolation trenches spacedapart in the y-direction are cut along the x-directions to formindividual memory cells of each NAND string. Isolation trenches spacedapart in the x-direction and along the y-direction are cut to formindividual NAND strings. These isolation trenches are eventually filledwith isolation oxide (not shown).

It can be seen that the above-described process has silicide of apredetermined thickness 350 formed in the memory cell regions while athicker silicide layer 350′ is formed in the select device region andthe peripheral circuit regions of the chip. In this way, the thicknessof the silicide layers among the various regions of the chip can beindependently optimized. In particular, the thickness of the silicidelayer 350′ for the slit contacts in the peripheral circuits can beincreased independent of the silicide layer 350 of the memory cells.Similarly, the silicide layer 350′ in the select transistor region isindependent increased with respect to the silicide layer 350 of thememory cells. In this case, the conductivity of the thinner metal layeris not significantly reduced because of the larger metal line therecompared with those at the memory cells.

The foregoing detailed description has been presented for purposes ofillustration and description. It is not intended to be exhaustive or tolimit the above to the precise form disclosed. Many modifications andvariations are possible in light of the above teaching. The describedembodiments were chosen in order to explain the principles involved andits practical application, to thereby enable others to best utilize thevarious embodiments and with various modifications as are suited to theparticular use contemplated. It is intended that the scope be defined bythe claims appended hereto.

1-9. (canceled)
 10. A method of forming a memory, comprising: forming amulti-layer slab on top of a semiconductor substrate with layerscorresponding to structures of an array of NAND strings, and wherein thelayer includes a first region for forming memory cells of the NANDstrings and a second region for forming select transistors andperipheral circuits components, and wherein a first polysilicon layer isdeposited as a top layer of the multi-layer slab; masking the firstpolysilicon layer with a mask layer that leaves unmasked areas indesignated areas among the second region; etching trenches in theunmasked areas; depositing a second polysilicon layer in the trenches;etching back the second polysilicon layer to the mask layer; depositinga first metal layer; annealing to form a first silicide layer betweenthe first metal layer and the second polysilicon layers interfacing withthe first metal layer; removing the first metal layer; removing the masklayer to expose the first polysilicon layer; depositing a second metallayer; and annealing to form a second silicide layer between the secondmetal layer and the first polysilicon layer.
 11. The method as in claim10, wherein: the peripheral circuits components include slit contacts;said etching back the second polysilicon layer to the mask layer alsocreates at each slit contact an exposed portion of a floating gatepolysilicon below the first polysilicon layer; and said annealing toform a first silicide layer between the first metal layer and the secondpolysilicon layers interfacing with the first metal layer also has thefirst silicide layer formed between the first metal layer and theexposed floating gate polysilicon.
 12. The method as in claim 10,wherein: the first and second metal layers are tungsten.
 13. The methodas in claim 10, wherein: the first polysilicon layer is for forming aportion of the control gates of the memory cells.
 14. The method as inclaim 10, wherein: the first polysilicon layer is doped.
 15. The methodas in claim 10, wherein: the second polysilicon layer is for formingpoly plugs that connect between the first polysilicon layer and afloating-gate polysilicon layer.
 16. A method of forming a memory havingmemory cells arranged in a three-dimensional pattern defined byrectangular coordinates having x, y and z-directions, said methodcomprising: forming a multi-layer slab on top of a semiconductorsubstrate in an x-y plane, the layers of the multi-layer slab beingstacked in the z-direction and corresponding to structures of an arrayin the x-y plane of NAND memory cells, and wherein the layers includes afirst region for forming memory cells of the NAND strings and a secondregion for forming select transistors and peripheral circuitscomponents, and wherein a first polysilicon layer is deposited as a toplayer of the multi-layer slab; masking the first polysilicon layer witha mask layer that leaves unmasked areas in designated areas among thesecond region; etching trenches in the unmasked areas; depositing asecond polysilicon layer in the trenches; etching back the secondpolysilicon layer to the mask layer; depositing a first metal layer;annealing to form a first silicide layer between the first metal layerand the second polysilicon layers interfacing with the first metallayer; removing the first metal layer; removing the mask layer to exposethe first polysilicon layer; depositing a second metal layer; andannealing to form a second silicide layer between the second metal layerand the first polysilicon layer.
 17. The method as in claim 16, wherein:the peripheral circuits components include slit contacts; said etchingback the second polysilicon layer to the mask layer also creates at eachslit contact an exposed portion of a floating gate polysilicon below thefirst polysilicon layer; and said annealing to form a first silicidelayer between the first metal layer and the second polysilicon layersinterfacing with the first metal layer also has the first silicide layerformed between the first metal layer and the exposed floating gatepolysilicon.
 18. The method as in claim 16, wherein: the first andsecond metal layers are tungsten.
 19. The method as in claim 16,wherein: the first polysilicon layer is for forming a portion of thecontrol gates of the memory cells.
 20. The method as in claim 16,wherein: the second polysilicon layer is for forming poly plugs thatconnect between the first polysilicon layer and a floating-gatepolysilicon layer.